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NXP Semiconductors /MIMXRT1011 /IOMUXC_GPR /GPR11

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Interpret as GPR11

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (M7_APC_AC_R0_CTRL_0)M7_APC_AC_R0_CTRL 0 (M7_APC_AC_R1_CTRL_0)M7_APC_AC_R1_CTRL 0 (M7_APC_AC_R2_CTRL_0)M7_APC_AC_R2_CTRL 0 (M7_APC_AC_R3_CTRL_0)M7_APC_AC_R3_CTRL 0LOCK_M7_APC_AC_R0_CTRL 0LOCK_M7_APC_AC_R1_CTRL 0LOCK_M7_APC_AC_R2_CTRL 0LOCK_M7_APC_AC_R3_CTRL

M7_APC_AC_R0_CTRL=M7_APC_AC_R0_CTRL_0, M7_APC_AC_R1_CTRL=M7_APC_AC_R1_CTRL_0, M7_APC_AC_R3_CTRL=M7_APC_AC_R3_CTRL_0, M7_APC_AC_R2_CTRL=M7_APC_AC_R2_CTRL_0

Description

GPR11 General Purpose Register

Fields

M7_APC_AC_R0_CTRL

Access control of memory region-0

0 (M7_APC_AC_R0_CTRL_0): No access protection

1 (M7_APC_AC_R0_CTRL_1): M7 debug protection enabled
M7_APC_AC_R1_CTRL

Access control of memory region-1

0 (M7_APC_AC_R1_CTRL_0): No access protection

1 (M7_APC_AC_R1_CTRL_1): M7 debug protection enabled
M7_APC_AC_R2_CTRL

Access control of memory region-2

0 (M7_APC_AC_R2_CTRL_0): No access protection

1 (M7_APC_AC_R2_CTRL_1): M7 debug protection enabled
M7_APC_AC_R3_CTRL

Access control of memory region-3

0 (M7_APC_AC_R3_CTRL_0): No access protection

1 (M7_APC_AC_R3_CTRL_1): M7 debug protection enabled
LOCK_M7_APC_AC_R0_CTRL

Lock M7_APC_AC_R0_CTRL field for changes
LOCK_M7_APC_AC_R1_CTRL

Lock M7_APC_AC_R1_CTRL field for changes
LOCK_M7_APC_AC_R2_CTRL

Lock M7_APC_AC_R2_CTRL field for changes
LOCK_M7_APC_AC_R3_CTRL

Lock M7_APC_AC_R3_CTRL field for changes

Links

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Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data